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INTEGRATED CIRCUITS
74ABT16373B 74ABTH16373B 16-bit transparent latch (3-State)
Product specification Supersedes data of 1995 Aug 03 IC23 Data Handbook 1998 Feb 27
Philips Semiconductors
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
FEATURES
* 16-bit transparent latch * Multiple VCC and GND pins minimize switching noise * Power-up 3-State * Live insertion/extraction permitted * Power-up reset * 3-State output buffers * 74ABTH16373B incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused inputs
When nOE is Low, the latched or transparent data appears at the outputs. When nOE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus. Two options are available, 74ABT16373B which does not have the bus-hold feature and 74ABTH16373B which incorporates the bus-hold feature.
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1E 1D0 1D1 GND 1D2 1D3 VCC 1D4 1D5 GND 1D6 1D7 2D0 2D1 GND 2D2 2D3 VCC 2D4 2D5 GND 2D6 2D7 2E
* Output capability: +64mA/-32mA * ICCL -19 mA maximum * Latch-up protection exceeds 500mA per JEDEC Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16373B high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16373B device is a dual octal transparent latch coupled to two sets of eight 3-State output buffers. The two sections of the device are controlled independently by Enable (nE) and Output Enable (nOE) control gates. The data on each set of D inputs are transferred to the latch outputs when the Latch Enable (nE) input is High. The latch remains transparent to the data inputs while nE is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. Each active-Low Output Enable (nOE) controls eight 3-State buffers independent of the latch operation.
1Q6 1Q7 2Q0 2Q1 GND 2Q2 2Q3 VCC 2Q4 2Q5 GND 2Q6 2Q7 2OE
SA00379
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ ICCL PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Quiescent su ly current supply CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-State Outputs disabled; VCC = 5.5V Outputs low; VCC = 5.5V TYPICAL 2.5 2.0 4 7 500 8 UNIT ns pF pF A mA
ORDERING INFORMATION
PACKAGES 48-Pin SSOP type III 48-Pin TSSOP type II 48-Pin SSOP type III 48-Pin TSSOP type II TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT16373B DL 74ABT16373B DGG 74ABTH16373B DL 74ABTH16373B DGG NORTH AMERICA BT16373B DL BT16373B DGG BH16373B DL BH16373B DGG DWG NUMBER SOT370-1 SOT362-1 SOT370-1 SOT362-1
1998 Feb 27
2
853-1751 19027
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
PIN DESCRIPTION
PIN NUMBER 47, 46, 44, 43, 41, 40, 38, 37, 36, 35, 33, 32, 30, 29, 27, 26 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 16, 17, 19, 20, 22, 23 1, 24 48, 25 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 SYMBOL 1D0 - 1D7 2D0 - 2D7 1Q0 - 1Q7 2Q0 - 2Q7 1OE, 2OE 1E, 2E GND VCC FUNCTION Data inputs
LOGIC SYMBOL (IEEE/IEC)
1OE 1E 2OE 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 4D 2 1EN C3 2EN C4 1 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23
Data outputs Output enable inputs (active-Low) Enable inputs (active-High) Ground (0V) Positive supply voltage
2E 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1
3D
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
LOGIC SYMBOL
47 46 44 43 41 40 38 37
2D2 2D3
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 48 1 1LE 1OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2D4 2D5 2D6 2D7
SA00380
2 36 3 35 5 33 6 32 8 30 9 29 11 27 12 26
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7 25 24 2LE 2OE 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
13
14
16
17
19
20
22
23
SA00044
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
nLE
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7
SA00046
1998 Feb 27
3
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
FUNCTION TABLE
INPUTS nOE L L L L L H H H= h= L= l= NC= X= Z= = nE H H L L H nDx L H i h X X Dn INTERNAL REGISTER L H L H NC NC Dn OUTPUTS nQ0 - nQ7 L H L H NC Z Z OPERATING MODE Enable and read register Latch and read register Hold Disable outputs
High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don't care High impedance "off" state High-to-Low E transition
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state DC output current Storage temperature range output in High state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -64 -65 to 150 mA C UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 PARAMETER MIN 4.5 0 2.0 0.8 -32 64 10 +85 MAX 5.5 VCC UNIT V V V V mA mA ns/V C
1998 Feb 27
4
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C MIN VIK VOH VOL VRST II Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH Low-level output voltage Power-up output voltage3 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5 5V; VI = VCC or GND 5.5V; VCC = 5.5V; VI = VCC or GND II Input leakage current 74ABTH16373B VCC = 5.5V; VI = VCC VCC = 5.5V; VI = 0 VCC = 4.5V; VI = 0.8V IHOLD Bus Hold current A inputs6 74ABTH16373B Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output current1 Output High leakage current VCC = 4.5V; VI = 2.0V VCC = 5.5V; VI = 0 to 5.5V IOFF IPU/IPD IOZH IOZL IO ICEX ICCH ICCL ICCZ ICC Additional supply current per input pin2 74ABT16373B Additional supply current per input pin2 74ABTH16373B Quiescent supply current VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = GND VCC = 5.5V; VO = 5.5V; VI = VIL or VIH VCC = 5.5V; VO = 0.0V; VI = VIL or VIH VCC = 5.5V; VO = 2.5V VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 Control pins Data pins5 50 -75 800 5.0 5.0 0.5 -0.5 -70 0.1 0.5 8 0.5 100 50 10 -10 -180 50 2 19 2 -50 100 50 10 -10 -180 50 2 19 2 A A A A mA A mA mA mA A 2.5 3.0 2.0 TYP -0.9 2.9 3.4 2.4 0.42 0.13 0 01 0.01 0.01 0.01 -1 0.55 0.55 1 1 1 -3 50 -75 A MAX -1.2 2.5 3.0 2.0 0.55 0.55 1 1 1 -5 Tamb = -40C to +85C MIN MAX -1.2 V V V V V V A A A A UNIT
Input leakage current g 74ABT16373B
5
100
100
ICC
0.5
1.5
1.5
mA
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1 to VCC = 5V 10% a transition time of up to 100sec is permitted. 5. Unused pins at VCC or GND. 6. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
5
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay nDx to nQx Propagation delay nE to nQx Output enable time to High and Low level Output disable time from High and Low level 2 1 4 5 4 5 1.5 1.1 1.6 1.3 1.2 1.3 1.9 1.7 Tamb = +25C VCC = +5.0V TYP 2.5 2.0 2.5 2.1 2.3 2.3 3.1 2.6 MAX 3.8 3.1 3.8 3.1 3.5 3.5 4.5 3.8 Tamb = -40 to +85C VCC = +5.0V 0.5V MIN 1.5 1.1 1.6 1.3 1.2 1.3 1.9 1.7 MAX 4.4 3.8 4.4 3.6 4.6 4.5 5.3 4.2 ns ns ns ns UNIT
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low nDx to nE Hold time, High or Low nDx to nE Enable pulse width High 3 3 1 1.0 1.0 0.5 0.5 2.5 Tamb = +25C VCC = +5.0V TYP 0.0 0.3 -0.2 0.0 1.0 Tamb = -40 to +85C VCC = +5.0V 0.5V MIN 1.0 1.0 0.5 0.5 2.5 ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V.
nE
VM
VM
VM
nDx
VM
VM
tw(H) tPHL nQx VM
tPLH tPLH nQx VM VM
tPHL
VM
SA00047
SA00048
Waveform 1.
Propagation Delay, Enable to Output, and Enable Pulse Width
Waveform 2. Propagation Delay for Data to Outputs
1998 Feb 27
6
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
nDx
nE
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
TEST CIRCUIT AND WAVEFORM
VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
PULSE GENERATOR
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
1998 Feb 27
EEEEEEEEEE EEE E EEEEEEEEEE EEE E EEEEEEEEEE EEE E
VM VM VM VM ts(H) th(H) ts(L) th(L) VM VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
nOE
VM tPZL
VM tPLZ
nQx
VM
VOL + 0.3V VOL
SA00049
SA00051
Waveform 3.
Data Setup and Hold Times
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
nOE
VM tPZH
VM tPHZ VOH VOH - 0.3V 0V
nQx
VM
SA00050
VIN D.U.T. RT
VOUT
Test Circuit for 3-State Outputs
VM
VM = 1.5V Input Pulse Definition
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT/H16 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00018
7
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
1998 Feb 27
8
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm
SOT362-1
1998 Feb 27
9
Philips Semiconductors
Product specification
16-bit transparent latch (3-State)
74ABT16373B 74ABTH16373B
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03491
Philips Semiconductors
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